Hierarchical constraint transformation using directed interval search for analog system synthesis
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Remembrance of circuits past: macromodeling by data mining in large analog design spaces
Proceedings of the 39th annual Design Automation Conference
ACTIF: a high-level power estimation tool for analog continuous-time filters
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Synthesis of analog and mixed-signal integrated electronic circuits
Formal engineering design synthesis
Performance trade-off analysis of analog circuits by normal-boundary intersection
Proceedings of the 40th annual Design Automation Conference
Support vector machines for analog circuit performance representation
Proceedings of the 40th annual Design Automation Conference
Performance Modeling of Analog Integrated Circuits Using Least-Squares Support Vector Machines
Proceedings of the conference on Design, automation and test in Europe - Volume 1
HOLMES: Capturing the Yield-Optimized Design Space Boundaries of Analog and RF Integrated Circuits
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Accuracy driven performance macromodeling of feasible regions during synthesis of analog circuits
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Deterministic approaches to analog performance space exploration (PSE)
Proceedings of the 42nd annual Design Automation Conference
Performance space modeling for hierarchical synthesis of analog integrated circuits
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Hierarchical performance macromodels of feasible regions for synthesis of analog and RF circuits
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Proceedings of the 43rd annual Design Automation Conference
Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
High-Level Power Minimization of Analog Sensor Interface Architectures
Integrated Computer-Aided Engineering
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