Performance space modeling for hierarchical synthesis of analog integrated circuits

  • Authors:
  • Georges Gielen;Trent McConaghy;Tom Eeckelaert

  • Affiliations:
  • Katholieke Universiteit Leuven, Leuven, Belgium;Katholieke Universiteit Leuven, Leuven, Belgium;Katholieke Universiteit Leuven, Leuven, Belgium

  • Venue:
  • Proceedings of the 42nd annual Design Automation Conference
  • Year:
  • 2005

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Abstract

Automated analog sizing is becoming an unavoidable solution for increasing analog design productivity. The complexity of typical analog SoC subsystems however calls for efficient methods that can handle design hierarchy, in terms of both performance estimation and hierarchical design optimization method. This paper discusses and compares recent developments in this area, with special emphasis on automated modeling and on multi-objective bottom-up hierarchical design.