MAELSTROM: efficient simulation-based synthesis for custom analog cells
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Remembrance of circuits past: macromodeling by data mining in large analog design spaces
Proceedings of the 39th annual Design Automation Conference
A layout-aware synthesis methodology for RF circuits
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
An rf synthesis flow toward fast parasitic closure
An rf synthesis flow toward fast parasitic closure
Device-level early floorplanning algorithms for RF circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal design of a CMOS op-amp via geometric programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance space modeling for hierarchical synthesis of analog integrated circuits
Proceedings of the 42nd annual Design Automation Conference
Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic Corners
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Classification of analog synthesis tools based on their architecture selection mechanisms
Integration, the VLSI Journal
A layout-aware analog synthesis procedure inclusive of dynamic module geometry selection
Proceedings of the 18th ACM Great Lakes symposium on VLSI
LASER: layout-aware analog synthesis environment on laker
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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An electrical and physical synthesis flow for high-speed analog and radio-frequency circuits is presented in this paper. Novel techniques aiming at fast parasitic closure are employed throughout the flow. Parasitic corners generated based on the earlier placement statistics are included for circuit resizing to enable parasitic robust designs. A performance-driven placement with simultaneous fast incremental global routing is proposed to achieve accurate parasitic estimation. Device tuning is utilized during layout to compensate for layout induced performance degradations. This methodology allows sophisticated macromodels of performances versus device variables and parasitics to be used during layout synthesis to make it truly performance-driven. Experimental results of a 4GHz LNA and a mixer demonstrate fast parasitic closure with this methodology.