DARWIN: CMOS opamp synthesis by means of a genetic algorithm
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Analysis and justification of a simple, practical 2 1/2-D capacitance extraction methodology
DAC '97 Proceedings of the 34th annual Design Automation Conference
MAELSTROM: efficient simulation-based synthesis for custom analog cells
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Optimal RF design using smart evolutionary algorithms
Proceedings of the 37th Annual Design Automation Conference
CYCLONE: automated design and layout of RF LC-oscillators
Proceedings of the 37th Annual Design Automation Conference
Numerical Optimization of Computer Models
Numerical Optimization of Computer Models
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
CAD solutions and outstanding challenges for mixed-signal and RFIC design
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Accurate Estimation of Parasitic Capacitances in Analog Circuits
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A high level language for pre-layout extraction in parasite-aware analog circuit synthesis
Proceedings of the 14th ACM Great Lakes symposium on VLSI
A two-layer library-based approach to synthesis of analog systems from VHDL-AMS specifications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fast and accurate parasitic capacitance models for layout-aware
Proceedings of the 41st annual Design Automation Conference
A synthesis flow toward fast parasitic closure for radio-frequency integrated circuits
Proceedings of the 41st annual Design Automation Conference
Languages for system specification
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Modeling Layout Effects for Sensitivity-Based Analog Circuit Optimization
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Performance space modeling for hierarchical synthesis of analog integrated circuits
Proceedings of the 42nd annual Design Automation Conference
Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic Corners
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A layout-aware analog synthesis procedure inclusive of dynamic module geometry selection
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Partitioning parameterized 45-degree polygons with constraint programming
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Simulation-Based Hybrid Optimization Technique for Low Noise Amplifier Design Automation
ICCS '07 Proceedings of the 7th international conference on Computational Science, Part IV: ICCS 2007
Improvement of ANNs Performance to Generate Fitting Surfaces for Analog CMOS Circuits
IWINAC '07 Proceedings of the 2nd international work-conference on Nature Inspired Problem-Solving Methods in Knowledge Engineering: Interplay Between Natural and Artificial Computation, Part II
A scalable σ-space based methodology for modeling process parameter variations in analog circuits
Microelectronics Journal
Electronic design automation using a unified optimization framework
Mathematics and Computers in Simulation
Mathematics and Computers in Simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
CEC'09 Proceedings of the Eleventh conference on Congress on Evolutionary Computation
Analog layout synthesis: recent advances in topological approaches
Proceedings of the Conference on Design, Automation and Test in Europe
LAYGEN II: automatic analog ICs layout generator based on a template approach
Proceedings of the 14th annual conference on Genetic and evolutionary computation
Routing analog ICs using a multi-objective multi-constraint evolutionary approach
Analog Integrated Circuits and Signal Processing
Template coding with LDS and applications of LDS in EDA
Analog Integrated Circuits and Signal Processing
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In this paper a layout-aware RF synthesis methodology is presented. The methodology combines the power of a differential evolution algorithm with cost function response modeling and integrated layout generation to synthesize RF Circuits efficiently, taking into account all layout parasitics during the circuit optimization. The proposed approach has successfully been applied to the design of a high-performance downconverter mixer circuit, proving the effectiveness of the implemented design methodology.