Layout-oriented synthesis of high performance analog circuits
DATE '00 Proceedings of the conference on Design, automation and test in Europe
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A high level language for pre-layout extraction in parasite-aware analog circuit synthesis
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Fast and accurate parasitic capacitance models for layout-aware
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This paper presents efficient and accurate techniques for modeling parasitic capacitances in analog CMOS circuits. A layout aware synthesis .ow using these parasitic models has been proposed. The fast parasitic estimation process replaces the time consuming steps of layout generation and extraction during synthesis. Results indicate that these models are extremelyfast and accurate.