Synthesis of high-performance analog circuits in ASTRX/OBLX
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automation of IC layout with analog constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimum CMOS stack generation with analog constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analog design for reuse - case study: very low-voltage sigma-delta modulator
Proceedings of the conference on Design, automation and test in Europe
An Introduction to Rapid System Prototyping
IEEE Transactions on Software Engineering
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Accurate Estimation of Parasitic Capacitances in Analog Circuits
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A high level language for pre-layout extraction in parasite-aware analog circuit synthesis
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Fast and accurate parasitic capacitance models for layout-aware
Proceedings of the 41st annual Design Automation Conference
Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic Corners
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A layout-aware analog synthesis procedure inclusive of dynamic module geometry selection
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Partitioning parameterized 45-degree polygons with constraint programming
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Analog layout generator for CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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