An O(n) algorithm for transistor stacking with performance constraints
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Synthesis tools for mixed-signal ICs: progress on frontend and backend strategies
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Width minimization of two-dimensional CMOS cells using integer programming
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Global stacking for analog circuits
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Optimal 2-D cell layout with integrated transistor folding
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
CMOS analog circuit stack generation with matching constraints
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Layout tools for analog ICs and mixed-signal SoCs: a survey
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Layout-oriented synthesis of high performance analog circuits
DATE '00 Proceedings of the conference on Design, automation and test in Europe
CLIP: integer-programming-based optimal layout synthesis of 2D CMOS cells
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Direct transistor-level layout for digital blocks
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Synthesis of analog and mixed-signal integrated electronic circuits
Formal engineering design synthesis
XPRESS: A Cell Layout Generator with Integrated Transistor Folding
EDTC '96 Proceedings of the 1996 European conference on Design and Test
A Layout Approach for Electrical and Physical Design Integration of High-Performance Analog Circuits
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
| Hi-index | 0.03 |
An algorithm for the automatic generation of full-stacked layouts in CMOS analog circuits is described in this paper. The set of stacks obtained is optimum with respect to a cost function which accounts for critical parasitics and device area minimization. Device interleaving and common-centroid patterns are automatically introduced when possible, and all symmetry and matching constraints are enforced. The algorithm is based on operations performed on a graph representation of circuit connectivity, exploiting the equivalence between stack generation and path partitioning in the circuit graph. Path partitioning is carried out in two phases: in the first phase, all paths are generated by a dynamic programming procedure. In the second phase, the optimum partition is selected by solving a clique problem. Original heuristics have been introduced, which preserve the optimality of the solution, while effectively improving the computational efficiency of the algorithm. The algorithm has been implemented in the “C” programming language. Many test cases have been run, and the quality of results is comparable to that of hand-made circuits. Results also demonstrate the effectiveness of the heuristics employed, even for relatively complex circuits