Integer and combinatorial optimization
Integer and combinatorial optimization
Optimal layout of CMOS functional arrays
25 years of DAC Papers on Twenty-five years of electronic design automation
25 years of DAC Papers on Twenty-five years of electronic design automation
The layout synthesizer: an automatic Netlist-to-Layout system
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
GENAC: an automatic cell synthesis tool
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Technology mapping for field-programmable gate arrays using integer programming
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A timing-driven data path layout synthesis with integer programming
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Logic-based 0-1 constraint programming
Logic-based 0-1 constraint programming
An O(n) algorithm for transistor stacking with performance constraints
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Width minimization of two-dimensional CMOS cells using integer programming
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
CLIP: an optimizing layout generator for two-dimensional CMOS cells
DAC '97 Proceedings of the 34th annual Design Automation Conference
Integer-programming-based layout synthesis of two-dimensional CMOS cells
Integer-programming-based layout synthesis of two-dimensional CMOS cells
SOLO: a generator of efficient layouts from optimized MOS circuit schematics
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Optimal 2-D cell layout with integrated transistor folding
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A Combined Pairing and Chaining Algorithm for CMOS Layout Generation
EDTC '96 Proceedings of the 1996 European conference on Design and Test
XPRESS: A Cell Layout Generator with Integrated Transistor Folding
EDTC '96 Proceedings of the 1996 European conference on Design and Test
A Hierarchical Technique for Minimum-Width Layout of Two-Dimensional CMOS Cells
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Near-Optimum Hierarchical Layout Synthesis of Two-Dimensional CMOS Cells
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Transistor Chaining in CMOS Leaf Cells of Planar Topology
GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
Optimum CMOS stack generation with analog constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Integer programming based topology selection of cell-level analog circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On over-the-cell channel routing with cell orientations consideration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exact and heuristic approaches to input vector control for leakage power reduction
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Standard cell routing via boolean satisfiability
Proceedings of the 49th Annual Design Automation Conference
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A novel technique, CLIP, is presented for the automatic generation of optimal layouts of CMOS cells in the two-dimensional (2D) style. CLIP is based on integer-linear programming (ILP) and solves both the width and height minimization problems for 2D cells. Width minimization is formulated in a precise form that combines all factors influencing the 2D cell width—transistor placement, diffusion sharing, and vertical interrow connections—in a common problem space; this space is then searched in a systematic manner by the branch-and-bound algorithms used by ILP solvers. For height minimization, cell height is modeled accurately in terms of the horizontal wire routing density, and a minimum-height layout is found from among all layouts of minimum width. For exact width minimization alone, CLIP's run times are in seconds for large circuits with 30 or more transistors. For both height and width optimization, CLIP is practical for circuits with up to 20 transistors. To extend CLIP to larger circuits, hierarchical methods are necessary. Since CLIP is optimum under the modeling assumptions, its layouts are significantly better than those generated by other, heuristic, layout tools.