A Combined Pairing and Chaining Algorithm for CMOS Layout Generation

Authors:
A. Josep Velasco;Xavier Marin;Jordi Carrabina;Rafael Peset Llopis
Affiliations:
Centre National de Microelectrònica-Universitat Autònoma de Barcelona, CNM-UAB, Campus UAB, 08193 Bellaterra, Spain;Centre National de Microelectrònica-Universitat Autònoma de Barcelona, CNM-UAB, Campus UAB, 08193 Bellaterra, Spain;Centre National de Microelectrònica-Universitat Autònoma de Barcelona, CNM-UAB, Campus UAB, 08193 Bellaterra, Spain;Philips Research Laboratories, Eindhoven, The Netherlands
Venue:
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Year:
1996

Citing 1
Cited 1

Principles of CMOS VLSI design: a systems perspective

Principles of CMOS VLSI design: a systems perspective

CLIP: integer-programming-based optimal layout synthesis of 2D CMOS cells

ACM Transactions on Design Automation of Electronic Systems (TODAES)

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Abstract

Most published chaining algorithms require a previous pairing step. Since an heuristical approach is used for pairing, the optimal pairing is not always found. A new algorithm is presented that combines pairing and chaining into one single step. This approach is based on Chi-Yi-Hwang et al's algorithm. Optimal results are always reached.