Automatic layout synthesis of leaf cells
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Journal of the ACM (JACM)
CLIP: integer-programming-based optimal layout synthesis of 2D CMOS cells
ACM Transactions on Design Automation of Electronic Systems (TODAES)
High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Exact combinatorial optimization methods for physical design of regular logic bricks
Proceedings of the 44th annual Design Automation Conference
On the History of the Minimum Spanning Tree Problem
IEEE Annals of the History of Computing
Standard Cell Like Via-Configurable Logic Block for Structured ASICs
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
Transistor-level layout of high-density regular circuits
Proceedings of the 2009 international symposium on Physical design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SAT based multi-net rip-up-and-reroute for manufacturing hotspot removal
Proceedings of the Conference on Design, Automation and Test in Europe
Physical synthesis onto a layout fabric with regular diffusion and polysilicon geometries
Proceedings of the 48th Design Automation Conference
Rule agnostic routing by using design fabrics
Proceedings of the 49th Annual Design Automation Conference
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We propose a flow for routing nets within a standard cell that 1) generates candidate routes for point-to-point segments; 2) finds conflicts (electrical shorts and geometric design rule violations) between candidate routes; and 3) solves a SAT instance producing a legal and complete routing for all nets in the standard cell. This approach enables routing automation for cutting-edge process technology nodes. We present how to make this technique more effective by introducing pruning techniques to reduce the work required in all three steps. We also show how we can further optimize routing quality within the SAT formulation through the use of successively more stringent constraints. Recent improvements in the speed of SAT solvers make such a formulation practical for even complex standard cells. A routing tool based on our SAT formulation is currently being used to route real industrial standard cell layouts. It demonstrates acceptable runtime and 89% coverage of our industrial standard cell library, including scan flip-flops, adders, and multiplexers. We also observe a significant reduction in amount of metal2 routing in comparison with industrial hand-crafted standard cells.