Optical proximity correction (OPC): friendly maze routing
Proceedings of the 41st annual Design Automation Conference
Maze routing with OPC consideration
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Detailed placement for improved depth of focus and CD control
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Pattern sensitive placement for manufacturability
Proceedings of the 2007 international symposium on Physical design
Efficient process-hotspot detection using range pattern matching
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Exact combinatorial optimization methods for physical design of regular logic bricks
Proceedings of the 44th annual Design Automation Conference
ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction
Proceedings of the 45th annual Design Automation Conference
An automatic optical-simulation-based lithography hotspot fix flow for post-route optimization
Proceedings of the 2009 international symposium on Physical design
Proceedings of the 48th Design Automation Conference
Standard cell routing via boolean satisfiability
Proceedings of the 49th Annual Design Automation Conference
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Manufacturing hotspots are the layout patterns which cause excessive difficulties to manufacturing process. Design rules are effective at handling sizing/spacing induced hotspots, but are inadequate at dealing with topological hotspots. In wire routings, existing approaches often remove the hotspots through iteratively ripping up and rerouting one net at a time guided by litho-simulations. This procedure can be very time-consuming because litho-simulation is typically very slow and the rerouting may result in new hotspots due to its heuristic nature. In this paper, we propose a new approach for improving the efficiency of hotspot removal. In our approach, multiple nets in each hotspot region are simultaneously ripped up and rerouted based on Boolean satisfiability (SAT). The hotspot patterns, which are described and stored in a pre-built library, are forbidden to appear in the reroute through SAT constraints. Since multiple nets are simultaneously processed and SAT can guarantee to find a feasible solution if it exists, our approach can greatly accelerate the convergence on manufacturability. Experimental results on benchmark circuits show that our approach can remove over 90% of the hotspots in less than one minute on circuits with more than 20K nets and hundreds of hotspots.