Gate sizing for constrained delay/power/area optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Introduction to Algorithms
Layout impact of resolution enhancement techniques: impediment or opportunity?
Proceedings of the 2003 international symposium on Physical design
Exploring regular fabrics to optimize the performance-cost trade-off
Proceedings of the 40th annual Design Automation Conference
Proceedings of the 2004 international symposium on Physical design
Optical proximity correction (OPC): friendly maze routing
Proceedings of the 41st annual Design Automation Conference
Design methodology for IC manufacturability based on regular logic-bricks
Proceedings of the 42nd annual Design Automation Conference
RADAR: RET-aware detailed routing using fast lithography simulations
Proceedings of the 42nd annual Design Automation Conference
Detailed placement for improved depth of focus and CD control
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Optimal cell flipping in placement and floorplanning
Proceedings of the 43rd annual Design Automation Conference
Detailed placement for leakage reduction using systematic through-pitch variation
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction
Proceedings of the 45th annual Design Automation Conference
Impact of lithography-friendly circuit layout
Proceedings of the 19th ACM Great Lakes symposium on VLSI
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SAT based multi-net rip-up-and-reroute for manufacturing hotspot removal
Proceedings of the Conference on Design, Automation and Test in Europe
Pattern sensitive placement perturbation for manufacturability
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dealing with IC manufacturability in extreme scaling
Proceedings of the International Conference on Computer-Aided Design
Methodology for standard cell compliance and detailed placement for triple patterning lithography
Proceedings of the International Conference on Computer-Aided Design
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When VLSI technology scales toward 45nm, the lithography wavelength stays at 193nm. This large gap results in strong refractive effects in lithography. Consequently, it is a huge challenge to reliably print layout features on wafers and the printing is more susceptible to lithographic process variations. Although resolution enhancement techniques can mitigate this manufacturability problem, their capabilities are overstretched by the continuous shrinking of VLSI feature size. On the other hand,the quality and robustness of lithography directly depend on layout patterns. Therefore, it becomes imperative to consider the manufacturability issue during layout design such that the burden of lithography process can be alleviated. In this paper, the problem of cell placement considering manufacturability is studied. Instead of designing a new cellplacer, our goal is to tune any existing cell placement solution to be lithography friendly. For this purpose, three algorithms are proposed, which are cell flipping algorithm, single row optimization approach and multiple row optimization approach. These algorithms are based on dynamic programming and graph theoretic approaches, and can provide different tradeoff between edge placement error (EPE)reduction and wirelength increase. Using lithography simulations, our experimental results on realistic netlists and cell library demonstrate that over 20% EPE reduction can be obtained by thenew approaches while only less than 1% additional wire is introduced.