ELIAD: efficient lithography aware detailed routing algorithm with compact and macro post-OPC printability prediction

Authors:
Minsik Cho;Kun Yuan;Yongchan Ban;David Z. Pan
Affiliations:
IBM T.J. Watson Research Center, Yorktown Heights, NY and Electrical and Computer Engineering Department, The University of Texas at Austin, Austin, TX;Electrical and Computer Engineering Department, The University of Texas at Austin, Austin, TX;Electrical and Computer Engineering Department, The University of Texas at Austin, Austin, TX;Electrical and Computer Engineering Department, The University of Texas at Austin, Austin, TX
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2009

Citing 20
Cited 4

Layout impact of resolution enhancement techniques: impediment or opportunity?

Proceedings of the 2003 international symposium on Physical design
Crosstalk-Constrained Maze Routing Based on Lagrangian Relaxation

ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Fast optical and process proximity correction algorithms for integrated circuit manufacturing

Fast optical and process proximity correction algorithms for integrated circuit manufacturing
Optical proximity correction (OPC): friendly maze routing

Proceedings of the 41st annual Design Automation Conference
RADAR: RET-aware detailed routing using fast lithography simulations

Proceedings of the 42nd annual Design Automation Conference
Unification of partitioning, placement and floorplanning

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Post-routing redundant via insertion for yield/reliability improvement

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Maze routing with OPC consideration

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Detailed placement for improved depth of focus and CD control

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Redundant-via enhanced maze routing for yield improvement

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Novel full-chip gridless routing considering double-via insertion

Proceedings of the 43rd annual Design Automation Conference
Process variation aware OPC with variational lithography modeling

Proceedings of the 43rd annual Design Automation Conference
Pattern sensitive placement for manufacturability

Proceedings of the 2007 international symposium on Physical design
Optimizing yield in global routing

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Wire density driven global routing for CMP variation and timing

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Efficient process-hotspot detection using range pattern matching

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
TROY: track router with yield-driven wire planning

Proceedings of the 44th annual Design Automation Conference
Accurate detection for process-hotspots with vias and incomplete specification

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multilevel Full-Chip Gridless Routing With Applications to Optical-Proximity Correction

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Predictive formulae for OPC with applications to lithography-friendly routing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Rapid layout pattern classification

Proceedings of the 16th Asia and South Pacific Design Automation Conference
AENEID: a generic lithography-friendly detailed router based on post-RET data learning and hotspot detection

Proceedings of the 48th Design Automation Conference
Simultaneous OPC- and CMP-aware routing based on accurate closed-form modeling

Proceedings of the 2013 ACM international symposium on International symposium on physical design

Quantified Score

Hi-index	0.04

Visualization

Abstract

In this paper, we present an efficient lithography aware detailed (ELIAD) router to enhance silicon image after optical proximity correction (OPC) in a correct-by-construction manner. We first quantitatively show that a pre-OPC litho-metric is highly uncorrelated with a post-OPC metric, which stresses the importance of a post-OPC litho-metric for design-time optimization. We then propose a compact post-OPC litho-metric for a detailed router (DR) based on statistical characterization, where the interferences among predefined litho-prone shapes are captured as a lookup table. Our litho-metric derived from the characterization shows high fidelity to the total edge placement error (EPE) in large scale, compared with Calibre OPC/optical rule check. Therefore, ELIAD powered by the proposed litho-metric can enhance the overall post-OPC printed silicon image. Experimental results on 65-nm industrial circuits show that ELIAD outperforms a rip-up/rerouting approach such as Resolution-enhancement-technique-Aware Detailed Routing with 8× more EPE hot spot reduction and 12× speedup. Moreover, compared with a conventional DR, ELIAD is only about 50% slower.