The R*-tree: an efficient and robust access method for points and rectangles
SIGMOD '90 Proceedings of the 1990 ACM SIGMOD international conference on Management of data
R-trees: a dynamic index structure for spatial searching
SIGMOD '84 Proceedings of the 1984 ACM SIGMOD international conference on Management of data
Fixing Antenna Problem by Dynamic Diode Dropping and Jumper Insertion
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Guest Editors' Introduction: Design for Yield and Reliability
IEEE Design & Test
Physical CAD changes to incorporate design for lithography and manufacturability
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Improved multilevel routing with redundant via placement for yield and reliability
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Redundant-via enhanced maze routing for yield improvement
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Novel full-chip gridless routing considering double-via insertion
Proceedings of the 43rd annual Design Automation Conference
Post-routing redundant via insertion and line end extension with via density consideration
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Conjugate conflict continuation graphs for multi-layer constrained via minimization
Information Sciences: an International Journal
Double-via-driven standard cell library design
Proceedings of the conference on Design, automation and test in Europe
High-performance routing at the nanometer scale
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
BoxRouter 2.0: architecture and implementation of a hybrid and robust global router
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Optimal post-routing redundant via insertion
Proceedings of the 2008 international symposium on Physical design
Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the 18th ACM Great Lakes symposium on VLSI
ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction
Proceedings of the 45th annual Design Automation Conference
BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Post-routing redundant via insertion with wire spreading capability
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Redundant via insertion with wire bending
Proceedings of the 2009 international symposium on Physical design
Redundant wire insertion for yield improvement
Proceedings of the 19th ACM Great Lakes symposium on VLSI
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Routing for manufacturability and reliability
IEEE Circuits and Systems Magazine
Enhanced double via insertion using wire bending
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal double via insertion with on-track preference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Register placement for high-performance circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Dead via minimization by simultaneous routing and redundant via insertion
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Simultaneous redundant via insertion and line end extension for yield optimization
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Nanometer-scale standard cell library for enhanced redundant via1 insertion rate
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Hi-index | 0.00 |
Reducing the yield loss due to via failure is one of the important problems in design for manufacturability. A well known and highly recommended method to improve via yield/reliability is to add redundant vias. In this paper we study the problem of post-routing redundant via insertion and formulate it as a maximum independent set (MIS) problem. We present an efficient graph construction algorithm to model the problem, and an effective MIS heuristic to solve the problem. The experimental results show that our MIS heuristic inserts more redundant vias and distributes them more uniformly among via layers than a commercial tool and an existing method. The number of inserted redundant vias can be increased by up to 21.24%. Besides, since redundant vias can be classified into on-track and off-track ones, and on-track ones have better electrical properties, we also present two methods (one is modified from the MIS heuristic, and the other is applied as a post processor) to increase the amount of on-track redundant vias. The experimental results indicate that both methods perform very well.