Nanometer-scale standard cell library for enhanced redundant via1 insertion rate

Authors:
Tsang-Chi Kan;Shih-Hsien Yang;Ting-Feng Chang;Shanq-Jang Ruan
Affiliations:
National Taiwan University of Science and Technology, Taipei, Taiwan Roc;Synopsys Inc., Taipei, Taiwan Roc;National Taiwan University of Science and Technology, Taipei, Taiwan Roc;National Taiwan University of Science and Technology, Taipei, Taiwan Roc
Venue:
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Year:
2011

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Abstract

Despite the rapid advances in process technology, via failure is still problematic in nanometer-scale semiconductor manufacturing. Adding redundant vias is the typical approach for improving yield and reliability. Standard cells are essential for increasing the insertion rate of redundant via1s in cell-based designs. This study proposes an efficient library check and staggered pin arrangement approach that considers different configurations of redundant vias such as double-via and rectangle-via in order to increase redundant via1 insertion rate. Moreover, the proposed standard cell library is easily implemented in all currently available routers. The experimental results reveal that the proposed library improves total inserted redundant vias, total inserted redundant via1s, and total run time by 20.5%, 33.3%, and 44.8%, respectively. Compared to conventional approach, the average via1 insertion rate in double-via pattern is improved by 14.8%, and the via1 insertion rate in rectangle-via pattern is achieved at 100%.