Cost based tradeoff analysis of standard cell designs
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
Neighbor selection for variance reduction in I_DDQ and other parametric data
Proceedings of the IEEE International Test Conference 2001
Architecting ASIC libraries and flows in nanometer era
Proceedings of the 40th annual Design Automation Conference
Exploring regular fabrics to optimize the performance-cost trade-off
Proceedings of the 40th annual Design Automation Conference
Synthesis for Manufacturability: A Sanity Check
Proceedings of the conference on Design, automation and test in Europe - Volume 2
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Nanometer-scale standard cell library for enhanced redundant via1 insertion rate
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Design for Manufacturability (DFM) is becoming increasingly important as process geometries shrink. Conventional design rule pass/fail is not adequate to quantify DFM compliance. Instead, metrics are needed to compare designs. Yield might be an ideal metric, but is difficult to calculate objectively without significant manufacturing data. This paper investigates the qualities that good metrics require and shows an example of an approach that seems promising.