A statistical static timing analysis considering correlations between delays
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Proceedings of the 38th annual Design Automation Conference
Intrinsic Leakage in Low-Power Deep Submicron CMOS ICs
Proceedings of the IEEE International Test Conference
Accurate pre-layout estimation of standard cell characteristics
Proceedings of the 41st annual Design Automation Conference
A Comprehensive Methodology for Noise Characterization of ASIC Cell Libraries
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
CAD for nanometer silicon design challenges and success
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
DFM Metrics for Standard Cells
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
A parametric approach for handling local variation effects in timing analysis
Proceedings of the 46th Annual Design Automation Conference
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
BDD decomposition for delay oriented pass transistor logic synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hi-index | 0.00 |
This paper is in response to the question 'ASIC Design the nm era - dead or alive' from an ASIC library architecture and library flow point of view. The authors believe it is certainly significantly harder to design in the nm era but ASIC design is not dead. ASIC Design is much more challenging in the nanometer era. This paper will present some of the main effects that have become significant in terms of library architecture and library creation flow. Some full chip level effects will be discussed. Example solutions to some of these dramatic trends will also be presented. This is presented in a 'stories from the trenches' format - from the team that architects and delivers TI ASIC libraries. The majority of the data presented comes from development of TI ASIC 130, 90 and 65nm libraries.