A practical methodology for the statistical design of complex logic products for performance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design for manufacturability in submicron domain
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
An efficient statistical analysis methodology and its application to high-density DRAMs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Subwavelength optical lithography: challenges and impact on physical design
ISPD '99 Proceedings of the 1999 international symposium on Physical design
System-level power optimization: techniques and tools
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The road to better reliability and yield embedded DFM tools
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Stay away from minimum design-rule values
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Design of robust global power and ground networks
Proceedings of the 2001 international symposium on Physical design
A system level memory power optimization technique using multiple supply and threshold voltages
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Characterizing Substrate Coupling in Deep-Submicron Designs
IEEE Design & Test
A Simple via Duplication Tool for Yield Enhancement
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Impact of Deep Submicron Technology on Dependability of VLSI Circuits
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Non-tree routing for reliability and yield improvement
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Performance-impact limited area fill synthesis
Proceedings of the 40th annual Design Automation Conference
On-chip power supply network optimization using multigrid-based technique
Proceedings of the 40th annual Design Automation Conference
Optimal voltage allocation techniques for dynamically variable voltage processors
Proceedings of the 40th annual Design Automation Conference
Proceedings of the 40th annual Design Automation Conference
Death, taxes and failing chips
Proceedings of the 40th annual Design Automation Conference
An effective capacitance based driver output model for on-chip RLC interconnects
Proceedings of the 40th annual Design Automation Conference
Blade and razor: cell and interconnect delay analysis using current-based models
Proceedings of the 40th annual Design Automation Conference
System-on-chip beyond the nanometer wall
Proceedings of the 40th annual Design Automation Conference
NORM: compact model order reduction of weakly nonlinear systems
Proceedings of the 40th annual Design Automation Conference
Nanometer design: place your bets
Proceedings of the 40th annual Design Automation Conference
Architecting ASIC libraries and flows in nanometer era
Proceedings of the 40th annual Design Automation Conference
Integration of DFM Techniques and Design Automation
DFT '96 Proceedings of the 1996 Workshop on Defect and Fault-Tolerance in VLSI Systems
Maximizing Wafer Productivity Through Layout Optimization
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Leakage Power Estimation for Deep Submicron Circuits in an ASIC Design Environment
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Hot-carrier-Induced Circuit Degradation for 0.18 µm CMOS Technology
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
A Hybrid PPC Method Based on the Empirical Etch Model for the 0.14µm DRAM Generation and Beyond
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
An Efficient Rule-Based OPC Approach Using a DRC Tool for 0.18µm ASIC
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
On-Chip Interconnect Inductance - Friend or Foe (Invited)
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Analysis of IR-Drop Scaling with Implications for Deep Submicron P/G Network Designs
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Elimination of false aggressors using the functional relationship for full-chip crosstalk analysis
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Benchmarks for Interconnect Parasitic Resistance and Capacitance
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Statistical estimation of leakage current considering inter- and intra-die process variation
Proceedings of the 2003 international symposium on Low power electronics and design
An MTCMOS design methodology and its application to mobile computing
Proceedings of the 2003 international symposium on Low power electronics and design
Proceedings of the 2003 international symposium on Low power electronics and design
Energy and peak-current per-cycle estimation at RTL
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power circuits and technology for wireless digital systems
IBM Journal of Research and Development
Floorplanning with power supply noise avoidance
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
IBM Journal of Research and Development
TCAD development for lithography resolution enhancement
IBM Journal of Research and Development
Beyond the conventional transistor
IBM Journal of Research and Development
CMOS design near the limit of scaling
IBM Journal of Research and Development
Process modeling for future technologies
IBM Journal of Research and Development
Nanotechnology goals and challenges for electronic applications
IEEE Transactions on Nanotechnology
IEEE Transactions on Nanotechnology
Filling algorithms and analyses for layout density control
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical timing analysis using bounds and selective enumeration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Digital Circuit Optimization via Geometric Programming
Operations Research
Proceedings of the Conference on Design, Automation and Test in Europe
Reliable network-on-chip design for multi-core system-on-chip
The Journal of Supercomputing
A new methodology of integrating high level synthesis and floorplan for soc design
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
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As silicon CMOS technology is scaled into the nanometer regime, the paradigm shift of computer-aided design (CAD) technology is indispensable to cope with two major challenges (i.e., the ever-increasing design complexity of gigascale integration and complicated physical effects inherent from the nanoscale technology). System-level design and verification methodologies manage the functional complexity, and manufacturing-aware design techniques control the nanoscale physical effects. In this highlight paper, most nanometer design issues are described and the issues related to the higher level of abstraction are summarized. Process variability can be controlled by statistical design, resolution enhancement, planarity control, and other manufacturing-aware design techniques. Continuously growing problems such as leakage power, signal integrity, and reliability are also discussed. Finally, technology CAD for future nanometer devices is presented. For successful nanometer silicon design, closer cooperation among the design, process technology, mask, and CAD communities are essential.