Accurate interconnect modeling: towards multi-million transistor chips as microwave circuits
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
An efficient statistical analysis methodology and its application to high-density DRAMs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Performance Improvement for High Speed Devices Using E-tests and the SPICE Model
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
New Challenges in Delay Testing of Nanometer, Multigigahertz Designs
IEEE Design & Test
CAD for nanometer silicon design challenges and success
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Power Estimation Under Uncertain Delays
Integrated Computer-Aided Engineering
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Contradictory trends in the industrial design environment have increased uncertainty while decreasing the tolerance to uncertainty. Worst case design techniques, still widely used in industry, do not provide the accuracy required to design under these conditions. On the other hand, statistical design techniques do provide a significant improvement in accuracy, by virtue of their "circuit adaptive" behavior, but at a substantial cost in computational effort. One practical solution to improving the accuracy of worst case design without sacrificing efficiency is considered here. It integrates an efficient statistical circuit simulator with worst case design tools into a hierarchical performance design process. It employs two stages of worst case analysis, calibrated with statistical circuit simulation, serving as filters to screen out circuits that easily meet their performance requirements. This focuses the use of statistical circuit simulation on those circuits for which the improved accuracy provides significant benefit. This methodology has been applied with outstanding results in design and manufacturing.