A practical methodology for the statistical design of complex logic products for performance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computing parametric yield adaptively using local linear models
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Response Surface Methodology: Process and Product in Optimization Using Designed Experiments
Response Surface Methodology: Process and Product in Optimization Using Designed Experiments
CAD for nanometer silicon design challenges and success
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Variation-tolerant non-uniform 3D cache management in die stacked multicore processor
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
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In this work, a new approach for the statistical worst case of full-chip circuit performance and parametric yield prediction, using both the Modified-Principal Component Analysis (MPCA) and the Gradient Method (GM), is proposed and verified. This method enables designers not only to predict the standard deviations of circuit performances but also track the circuit performances associated with the process shift by measuring E-tests. This new method is validated experimentally during the development and production of high density DRAMs. Our contributions to statistical circuit design are as follows: 1) a method for directly generating a parametrized model associated with electrical test data 2) the first application to high density DRAMs using the true statistical method