A practical methodology for the statistical design of complex logic products for performance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Embedded software-based self-testing for SoC design
Proceedings of the 39th annual Design Automation Conference
VHDL: Analysis and Modeling of Digital Systems
VHDL: Analysis and Modeling of Digital Systems
A scalable software-based self-test methodology for programmable processors
Proceedings of the 40th annual Design Automation Conference
Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Design for Variability in DSM Technologies
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Statistical delay computation considering spatial correlations
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing-based delay test for screening small delay defects
Proceedings of the 43rd annual Design Automation Conference
A System-layer Infrastructure for SoC Diagnosis
Journal of Electronic Testing: Theory and Applications
Exploiting MOEA to automatically geneate test programs for path-delay faults in microprocessors
Evo'08 Proceedings of the 2008 conference on Applications of evolutionary computing
Statistical path selection for at-speed test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On the Application of Dynamic Scan Chain Partitioning for Reducing Peak Shift Power
Journal of Electronic Testing: Theory and Applications
Post-silicon bug detection for variation induced electrical bugs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Effective diagnostic pattern generation strategy for transition-delay faults in full-scan SOCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Evolution of test programs exploiting a FSM processor model
EvoApplications'11 Proceedings of the 2011 international conference on Applications of evolutionary computation - Volume Part II
Journal of Electronic Testing: Theory and Applications
Flip-flop selection for partial enhanced scan to reduce transition test data volume
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A high-precision on-chip path delay measurement architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
AC-plus scan methodology for small delay testing and characterization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Less predictable path delays and many paths with delays close to the clock period are the main trends affecting the delay testability of deep-submicron designs. This article examines the challenges in meeting the quality requirements of gigascale integration, and explores functional testing as well as statistical models and methods that could alleviate some of those problems.