Power Supply Noise Monitor for Signal Integrity Faults
Proceedings of the conference on Design, automation and test in Europe - Volume 2
New Challenges in Delay Testing of Nanometer, Multigigahertz Designs
IEEE Design & Test
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Proceedings of the 42nd annual Design Automation Conference
Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip
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ACM Transactions on Design Automation of Electronic Systems (TODAES)
Impact of supply voltage variations on full adder delay: analysis and comparison
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Understanding the effect of process variations on the delay of static and domino logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Post-silicon bug detection for variation induced electrical bugs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Robust Coupling Delay Test Sets
Journal of Electronic Testing: Theory and Applications
On the optimality of K longest path generation algorithm under memory constraints
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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The performance of deep submicron designs can be affected by various parametric variations, manufacturing defects, noise or modeling errors that are all statistical in nature. In this paper, we propose a methodology to capture the effects of these statistical variations on circuit performance. It incorporates statistical information into timing analysis to compute the performance sensitivity of internal signals subject to a given type of defect, noise or variation sources. Next, we propose a novel path and segment selection methodology for delay testing based on the results of statistical performance sensitivity analysis. The objective of path/segment selection is to identify a small set of paths and segments such that the delay tests for the selected paths/segments guarantee the detection of performance failure. We apply the proposed path selection technique for selection of a set of paths for dynamic timing analysis considering power supply noise effects. Our experimental results demonstrate the difference in estimated circuit performance for the case when power supply noise effects are considered versus when these effects are ignored. Thus, they indicate the need for considering power supply noise effects on delays during path selection and dynamic timing analysis.