A variable observation time method for testing delay faults
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Delay Fault Coverage Enhancement Using Variable Observation Times
Journal of Electronic Testing: Theory and Applications
High speed CMOS design styles
Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits
Journal of Electronic Testing: Theory and Applications
Design issues for dynamic voltage scaling
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Model and analysis for combined package and on-chip power grid simulation
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Enhancing test efficiency for delay fault testing using multiple-clocked schemes
Proceedings of the 39th annual Design Automation Conference
IC power distribution challenges
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Functionally Testable Path Delay Faults on a Microprocessor
IEEE Design & Test
Test Generation for Global Delay Faults
Proceedings of the IEEE International Test Conference on Test and Design Validity
Fault Coverage Analysis for Physically-Based CMOS Bridging Faults at Different Power Supply Voltages
Proceedings of the IEEE International Test Conference on Test and Design Validity
Detecting Delay Flaws by Very-Low-Voltage Testing
Proceedings of the IEEE International Test Conference on Test and Design Validity
Delay Testing of Digital Circuits by Output Waveform Analysis
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Very-Low-Voltage Testing for Weak CMOS Logic ICs
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Proceedings of the 40th annual Design Automation Conference
Segment delay faults: a new fault model
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
On Structural vs. Functional Testing for Delay Faults
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
IEEE Transactions on Computers
Modeling and Simulation of Time Domain Faults in Digital Systems
IOLTS '04 Proceedings of the International On-Line Testing Symposium, 10th IEEE
A Two-Level Power-Grid Model for Transient Current Testing Evaluation
Journal of Electronic Testing: Theory and Applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Journal of Electronic Testing: Theory and Applications
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This paper addresses the modeling and simulation of power supply voltage transients (驴 VDD) in digital SoC (Systems on a Chip), namely their impact on SoC core's performance. The goal is to verify, in a cost-effective way, core's fault tolerance to this disturbance, aiming at EMI/EMC standard compliance. The two key parameters are the time slack and the defect size. A top-down approach is used to introduce an innovative fault injection and simulation technique. In fact, fault simulation is carried out either by using faulty delays (defect size as a function of 驴 VDD magnitude) in the CUT (Core Under Test) and nominal time excitation rate, or by using a fault-free CUT description and faster test application times (speed-up proportional to 驴 VDD magnitude). A bottom-up approach, using electrical simulation, is extensively used to demonstrate the adequacy of exploiting this duality between time excitation and delay response, for combinational CUT. We refer this duality as the "accordion" effect. For sequential circuits, and for pipeline circuits, it is shown that the tolerance to 驴 VDD disturbances is significantly lower than the one observed in combinational CUT, due to de-synchronization effects in storage elements. This effect depends on the clock distribution network and is a consequence of differently delayed responses of the CUT and of the clock network. Results are demonstrated using basic infrastructures and ISCAS benchmark circuits.