SIGMA: a simulator for segment delay faults
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Fast identification of untestable delay faults using implications
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays
IEEE Transactions on Computers
Multiple Scan Chain Design for Two-Pattern Testing
Journal of Electronic Testing: Theory and Applications
ENHANCED DELAY DEFECT COVERAGE WITH PATH-SEGMENTS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Generation for Path-Delay Faults in One-dimensional Iterative Logic Arrays
ITC '00 Proceedings of the 2000 IEEE International Test Conference
TESTING OF CRITICAL PATHS FOR DELAY FAULTS
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Color Counting and its Application to Path Delay Fault Coverage
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors
Journal of Electronic Testing: Theory and Applications
On Selecting Testable Paths in Scan Designs
Journal of Electronic Testing: Theory and Applications
Accurate Path Delay Fault Coverage is Feasible
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Scalable Delay Fault BIST for Use with Low-Cost ATE
Journal of Electronic Testing: Theory and Applications
Implicit deductive fault simulation for complex delay fault models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient techniques for transition testing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip
Journal of Electronic Testing: Theory and Applications
On effective criterion of path selection for delay testing
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Propagation delay fault: a new fault model to test delay faults
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Transition path delay faults: a new path delay fault model for small and large delay defects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
ATPG-XP: test generation form maximal crosstalk-induced faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Deterministic broadside test generation for transition path delay faults
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Post-silicon bug detection for variation induced electrical bugs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
a fuzzy model for path delay fault detection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A multilevel fault model for integrated parallel fault-tolerant systems
Concurrency and Computation: Practice & Experience
Computing two-pattern test cubes for transition path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We propose a segment delay fault model to represent any general delay defect ranging from a spot defect to a distributed defect. The segment length, L, is a parameter that can be chosen based on available statistics about the types of manufacturing defects. Once L is chosen, the fault list contains all segments of length L and paths whose entire lengths are less than L. Both rising and falling transitions at the origin of segments are considered. Choosing segments of a small length can prevent an explosion of the number of faults considered. At the same time, a defect over a segment may be large enough to affect any path passing through it. We present an efficient algorithm to compute the number of segments of any possible length in a circuit. We define various classes of segment delay fault tests-robust, transition, and non-robust-that offer a trade-off between fault coverage and quality.