Implicit deductive fault simulation for complex delay fault models

Authors:
Jayant V. Deodhar;Spyros Tragoudas
Affiliations:
Texas Development Center, Intel Corporation, Austin, TX;Department of Electrical and Computer Engineering, Southern Illinois University, Carbondale, IL
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2004

Citing 10
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Abstract

This paper introduces an implicit version of the well-known deductive fault simulation technique suitable to delay fault models with an exponential number of faults. The proposed method calculates the fault coverage by generating lists of entities for each line during a single topological circuit traversal. Each stored entity only contains a number and a subset of the test vectors. No delay faults are stored, and no special data structures are required. There are significant differences between the presented implicit method and fault coverage using deductive fault simulation. The method is shown to be effective for delay the path and segment delay fault models.