Implicit grading of multiple path delay faults

Authors:
Saravanan Padmanaban;Spyros Tragoudas
Affiliations:
Intel Corporation, Hillsboro, OR;Southern Illinois University, Carbondale, IL
Venue:
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Year:
2006

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Abstract

The problem of fault grading for multiple path delay faults is introduced and a method of obtain exact coverage is presented. The faults are represented and manipulated as combinational sets using zero-suppressed binary decision diagrams. The presented methodology for fault grading uses only a polynomial number of zero-suppressed binary decision diagram operations. The efficiency of the proposed method is demonstrated by the experimental results on the ISCAS'85 and ISCAS'89 benchmarks.