Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
ATPG tools for delay faults at the functional level
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test Generation for Path Delay Faults Using Binary Decision Diagrams
IEEE Transactions on Computers
Generation of Compact Delay Tests by Multiple-Path Activation
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
A Method to Derive Compact Test Sets for Path Delay Faults in Combinational Circuits
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
ATPG for Path Delay Faults without Path Enumeration
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Using BDDs and ZBDDs for Efficient Identification of Testable Path Delay Faults
Proceedings of the conference on Design, automation and test in Europe - Volume 1
NEST: a nonenumerative test generation method for path delay faults in combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Classification and identification of nonrobust untestable path delay faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A fast nonenumerative automatic test pattern generator for path delay faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IGRAINE-an Implication GRaph-bAsed engINE for fast implication, justification, and propagation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test enrichment for path delay faults using multiple sets of target faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exact path delay fault coverage with fundamental ZBDD operations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Implicit grading of multiple path delay faults
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation
Journal of Electronic Testing: Theory and Applications
Exploiting MOEA to automatically geneate test programs for path-delay faults in microprocessors
Evo'08 Proceedings of the 2008 conference on Applications of evolutionary computing
Recursive pseudo-exhaustive two-pattern generation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Techniques to prioritize paths for diagnosis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We present a function-based nonenumerative automatic test pattern generation (ATPG)methodology for detecting path delay faults (PDFs). The proposed technique consists of a number of topological circuit traversals during each a linear number of Boolean functions is generated per circuit line. From each such function we derive a test that detects many PDFs. The two major strengths of the approach, that stem from the function-based formulations used, are very compact test sets, and scalability in test efficiency. The performance of an implementation based on binary decision diagrams is evaluated and compared with existing compact methods to demonstrate the superiority of the proposed method.