Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Zero-suppressed BDDs for set manipulation in combinatorial problems
DAC '93 Proceedings of the 30th international Design Automation Conference
Digital sensitivity: predicting signal interaction using functional analysis
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Fast identification of untestable delay faults using implications
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Worst and Best Irredundant Sum-of-Products Expressions
IEEE Transactions on Computers
Test Generation for Path Delay Faults Using Binary Decision Diagrams
IEEE Transactions on Computers
Testing of critical paths for delay faults
Proceedings of the IEEE International Test Conference 2001
Efficient Identification of Non-Robustly Untestable Path Delay Faults
Proceedings of the IEEE International Test Conference
Generation of Compact Delay Tests by Multiple-Path Activation
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
A Method to Derive Compact Test Sets for Path Delay Faults in Combinational Circuits
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
An Efficient Method to Identify Untestable Path Delay Faults
ATS '01 Proceedings of the 10th Asian Test Symposium
Path delay test compaction with process variation tolerance
Proceedings of the 42nd annual Design Automation Conference
Function-based compact test pattern generation for path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
NEST: a nonenumerative test generation method for path delay faults in combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast factorization method for implicit cube set representation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Classification and identification of nonrobust untestable path delay faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A fast nonenumerative automatic test pattern generator for path delay faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IGRAINE-an Implication GRaph-bAsed engINE for fast implication, justification, and propagation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Primitive path delay faults: identification and their use in timing analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test enrichment for path delay faults using multiple sets of target faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exact path delay fault coverage with fundamental ZBDD operations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Critical path selection for delay fault testing based upon a statistical timing model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient identification of (critical) testable path delay faults using decision diagrams
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics
Journal of Electronic Testing: Theory and Applications
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A new framework for generating test sets with high test efficiency for path delay faults (PDFs) is presented. The proposed method is based on a data structure that can implicitly represent all sensitizable PDFs in a circuit, along with all their corresponding tests. A path and test implicit method to construct such a data structure, for various path sensitization types, is presented. It uses zero-suppressed binary decision diagram (ZBDD) representations of irredundant sum-of-products (ISOPs), and requires only a polynomial number of standard ZBDD operations. Consequently, an ATPG algorithm that can exploit the properties of the proposed structure to derive tests with maximal test efficiency is presented. The obtained experimental results on the ISCAS'85 and enhanced full-scanned version of the ISCAS'89 benchmarks demonstrate that the proposed framework is scalable in terms of test efficiency and can generate compact test sets for critical PDFs.