Estimating path delay distribution considering coupling noise
Proceedings of the 17th ACM Great Lakes symposium on VLSI
A delay fault model for at-speed fault simulation and test generation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Exploring linear structures of critical path delay faults to reduce test efforts
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Fast second-order statistical static timing analysis using parameter dimension reduction
Proceedings of the 44th annual Design Automation Conference
Variation-aware performance verification using at-speed structural test and statistical timing
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation
Journal of Electronic Testing: Theory and Applications
Statistical path selection for at-speed test
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Bound-based identification of timing-violating paths under variability
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Statistical multilayer process space coverage for at-speed test
Proceedings of the 46th Annual Design Automation Conference
Critical Path Selection for Delay Testing Considering Coupling Noise
Journal of Electronic Testing: Theory and Applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Adjustment-based modeling for timing analysis under variability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal test margin computation for at-speed structural test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Pre-ATPG path selection for near optimal post-ATPG process space coverage
Proceedings of the 2009 International Conference on Computer-Aided Design
Statistical path selection for at-speed test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics
Journal of Electronic Testing: Theory and Applications
Graph partition based path selection for testing of small delay defects
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Optimal statistical chip disposition
Proceedings of the International Conference on Computer-Aided Design
Journal of Electronic Testing: Theory and Applications
Efficient Pattern Generation for Small-Delay Defects Using Selection of Critical Faults
Journal of Electronic Testing: Theory and Applications
Order statistics for correlated random variables and its application to at-speed testing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Critical path selection is an indispensable step for testing of small-size delay defects. Historically, this step relies on the construction of a set of worst-case paths, where the timing lengths of the paths are calculated based upon discrete-valued timing models. The assumption of discrete-valued timing models may become invalid for modeling delay effects in the deep submicron domain, where the effects of timing defects and process variations are often statistical in nature. This paper studies the problem of critical path selection for testing small-size delay defects, assuming that circuit delays are statistical. We provide theoretical analysis to demonstrate that the new path-selection problem consists of two computationally intractable subproblems. Then, we discuss practical heuristics and their performance with respect to each subproblem. Using a statistical defect injection and timing-simulation framework, we present experimental results to support our theoretical analysis.