Proceedings of the 39th annual Design Automation Conference
On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design
ITC '04 Proceedings of the International Test Conference on International Test Conference
K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits
ITC '04 Proceedings of the International Test Conference on International Test Conference
Evaluation of the Quality of N-Detect Scan ATPG Patterns on a Processor
ITC '04 Proceedings of the International Test Conference on International Test Conference
ALAPTF: A NEW TRANSITION FAULTMODEL AND THE ATPG ALGORITHM
ITC '04 Proceedings of the International Test Conference on International Test Conference
On N-Detect Pattern Set Optimization
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Test-Pattern Grading and Pattern Selection for Small-Delay Defects
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
Critical Path Selection for Delay Test Considering Coupling Noise
ETS '09 Proceedings of the 2009 European Test Symposium
Effective and Efficient Test Pattern Generation for Small Delay Defect
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the Conference on Design, Automation and Test in Europe
Circuit Topology-Based Test Pattern Generation for Small-Delay Defects
ATS '10 Proceedings of the 2010 19th IEEE Asian Test Symposium
Critical path selection for delay fault testing based upon a statistical timing model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Layout-Aware Critical Path Delay Test Under Maximum Power Supply Noise Effects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Testing for small-delay defects (SDDs) has become necessary as technology further scales. Existing tools and methodologies for generating SDD patterns suffer from: limited long-paths sensitization capability, overwhelming pattern volume, time-consuming pattern generation process, and vague evaluations of pattern quality. Such situation places patterns in a dilemma where the generation and application effort are huge yet the results cannot reflect the physical phenomena clearly enough for correct binning and diagnosis. In this paper, we focus on establishing a pattern generation flow that produces patterns of high application value. Firstly, critical faults are identified in order to generate high-quality original pattern repository with n-detect ATPG.A novelpattern evaluation and selection method that further minimizes pattern count while maintaining the SDD detection ability is then presented. Top-off ATPG is then performed to ensure meeting the target fault coverage. Along with the flow, multiple evaluation metrics are also proposed to measure the pattern's efficiency on SDD coverage, unique SDD detection, detectable SDD size, long path distribution, etc. Experimental results demonstrate that the proposed critical fault-based method improves long path sensitization efficiency by 2.5脳 without impairing its average delay and saves approximately 80 % CPU runtime compared with total fault-based method. Comparing with timing-aware ATPG, the generated pattern set detects equivalent or even more SDDs with significantly reduced pattern count.