Timing-based delay test for screening small delay defects
Proceedings of the 43rd annual Design Automation Conference
A novel framework for faster-than-at-speed delay test considering IR-drop effects
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Modeling Power Supply Noise in Delay Testing
IEEE Design & Test
Variation-aware performance verification using at-speed structural test and statistical timing
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
State persistence: a property for guiding test generation
Proceedings of the 19th ACM Great Lakes symposium on VLSI
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
A novel faster-than-at-speed transition-delay test method considering IR-drop effects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical path selection for at-speed test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Path selection for transition path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hazard-based detection conditions for improved transition path delay fault coverage
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Seed selection in LFSR-reseeding-based test compression for the detection of small-delay defects
Proceedings of the Conference on Design, Automation and Test in Europe
Optimal statistical chip disposition
Proceedings of the International Conference on Computer-Aided Design
Efficient Pattern Generation for Small-Delay Defects Using Selection of Critical Faults
Journal of Electronic Testing: Theory and Applications
Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths
Proceedings of the Conference on Design, Automation and Test in Europe
Generation of mixed test sets for transition faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Broadside and skewed-load tests under primary input constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test compaction for small-delay defects using an effective path selection scheme
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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To detect the smallest delay faults at a fault site, the longest path(s) through it must be tested at full speed. Existing test generation tools are inefficient in automatically identifying the longest testable paths due to the high computational complexity. In this work a test generation methodology for scan-based synchronous sequential circuits is presented, under two at-speed test strategies used in industry. The two strategies are compared and the test generation efficiency is evaluated on ISCAS89 benchmark circuits and industrial designs. Experiments show that testing transition faults through the longest paths can be done in reasonable test set size.