IEEE Transactions on Computers - Special issue on fault-tolerant computing
Reducing Test Dat Volume Using LFSR Reseeding with Seed Compression
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Achieving high encoding efficiency with partial dynamic LFSR reseeding
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Compressing Functional Tests for Microprocessors
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits
ITC '04 Proceedings of the International Test Conference on International Test Conference
An Economic Analysis and ROI Model for Nanometer Test
ITC '04 Proceedings of the International Test Conference on International Test Conference
ALAPTF: A NEW TRANSITION FAULTMODEL AND THE ATPG ALGORITHM
ITC '04 Proceedings of the International Test Conference on International Test Conference
Enhanced Timing-Based Transition Delay Testing for Small Delay Defects
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Timing-based delay test for screening small delay defects
Proceedings of the 43rd annual Design Automation Conference
Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects
ATS '06 Proceedings of the 15th Asian Test Symposium
A Seed-Selection Method to Increase Defect Coverage for LFSR-Reseeding-Based Test Compression
ETS '07 Proceedings of the 12th IEEE European Test Symposium
Test-Pattern Grading and Pattern Selection for Small-Delay Defects
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
Test data compression based on input-output dependence
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test-Quality/Cost Optimization Using Output-Deviation-Based Reordering of Test Patterns
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Secure JTAG Implementation Using Schnorr Protocol
Journal of Electronic Testing: Theory and Applications
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Test data volume and test application time are major concerns for large industrial circuits. In recent years, many compression techniques have been proposed and evaluated using industrial designs. However, these methods do not target sequence- or timing-dependent failures while compressing the test patterns. Timing-related failures in high-performance integrated circuits are now increasingly dominated by small-delay defects (SDDs). We present a SDD-aware seed-selection technique for LFSR-reseeding-based test compression. Experimental results show that significant test-pattern-quality increase can be achieved when seeds are selected to target SDDs.