Scan Test Response Compaction Combined with Diagnosis Capabilities
Journal of Electronic Testing: Theory and Applications
Deviation-based LFSR reseeding for test-data compression
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fully X-tolerant, very high scan compression
Proceedings of the 47th Design Automation Conference
Seed selection in LFSR-reseeding-based test compression for the detection of small-delay defects
Proceedings of the Conference on Design, Automation and Test in Europe
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This paper describes an Economic and Return-on- Investment (RoI) model for a test methodology that ensures product quality for logic devices that are in the 130 nm technology node and below. We describe the key components of the nanometer test methodology (NTM) and how it drives the model. In addition to ensuring product quality we address the cost of test and time to volume and how both factors can be improved. Examples from realistic scenarios are provided to illustrate the net savings from the proposed NTM using this model.