K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits
ITC '04 Proceedings of the International Test Conference on International Test Conference
An Economic Analysis and ROI Model for Nanometer Test
ITC '04 Proceedings of the International Test Conference on International Test Conference
ALAPTF: A NEW TRANSITION FAULTMODEL AND THE ATPG ALGORITHM
ITC '04 Proceedings of the International Test Conference on International Test Conference
Enhanced Timing-Based Transition Delay Testing for Small Delay Defects
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Timing-based delay test for screening small delay defects
Proceedings of the 43rd annual Design Automation Conference
Selecting High-Quality Delay Tests for Manufacturing Test and Debug
DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects
ATS '06 Proceedings of the 15th Asian Test Symposium
ATS '06 Proceedings of the 15th Asian Test Symposium
Automatic Generation of Instructions to Robustly Test Delay Defects in Processors
ETS '07 Proceedings of the 12th IEEE European Test Symposium
IEEE Design & Test
Variation-aware performance verification using at-speed structural test and statistical timing
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Transition path delay faults: a new path delay fault model for small and large delay defects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical path selection for at-speed test
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A new delay test based on delay defect detection within slack intervals (DDSI)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test-Quality/Cost Optimization Using Output-Deviation-Based Reordering of Test Patterns
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Non-Enumerative Technique for Measuring Path Correlation in Digital Circuits
Journal of Electronic Testing: Theory and Applications
Small-delay-fault ATPG with waveform accuracy
Proceedings of the International Conference on Computer-Aided Design
Efficient Pattern Generation for Small-Delay Defects Using Selection of Critical Faults
Journal of Electronic Testing: Theory and Applications
Test compaction for small-delay defects using an effective path selection scheme
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Timing-related defects are major contributors to test escapes and in-field reliability problems for very-deep submicrometer integrated circuits. Small delay variations induced by crosstalk, process variations, power-supply noise, as well as resistive opens and shorts can potentially cause timing failures in a design, thereby leading to quality and reliability concerns. We present a test-grading technique that uses the method of output deviations for screening small-delay defects (SDDs). A new gate-delay defect probability measure is defined to model delay variations for nanometer technologies. The proposed technique intelligently selects the best set of patterns for SDD detection from an n-detect pattern set generated using timing-unaware automatic test-pattern generation (ATPG). It offers significantly lower computational complexity and excites a larger number of long paths compared to a current generation commercial timing-aware ATPG tool. Our results also show that, for the same pattern count, the selected patterns provide more effective coverage ramp-up than timing-aware ATPG and a recent patternselection method for random SDDs potentially caused by resistive shorts, resistive opens, and process variations.