Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects

Authors:
Xijiang Lin;Kun-Han Tsai;Chen Wang;Mark Kassab;Janusz Rajski;Takeo Kobayashi;Randy Klingenberg;Yasuo Sato;Shuji Hamada;Takashi Aikyo
Affiliations:
Mentor Graphics Corporation, Wilsonville, OR 97070, USA;Mentor Graphics Corporation, Wilsonville, OR 97070, USA;Mentor Graphics Corporation, Wilsonville, OR 97070, USA;Mentor Graphics Corporation, Wilsonville, OR 97070, USA;Mentor Graphics Corporation, Wilsonville, OR 97070, USA;Mentor Graphics Corporation, Wilsonville, OR 97070, USA;Mentor Graphics Corporation, Wilsonville, OR 97070, USA;Semiconductor Technology Academic Research Center, Yokohama, Japan;Semiconductor Technology Academic Research Center, Yokohama, Japan;Semiconductor Technology Academic Research Center, Yokohama, Japan
Venue:
ATS '06 Proceedings of the 15th Asian Test Symposium
Year:
2006

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Abstract

Power of scan operation is dominant factor. This paper proposed the structure to reduce scan power totally. The total scan power reduction architecture uses a duplicated transition monitoring window and sub-scan chains. Experimental results show 60% ...