Very-Low-Voltage Testing for Weak CMOS Logic ICs
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Scan-Based Transition Fault Testing " Implementation and Low Cost Test Challenges
ITC '02 Proceedings of the 2002 IEEE International Test Conference
High-Frequency, At-Speed Scan Testing
IEEE Design & Test
Reducing Pattern Delay Variations for Screening Frequency Dependent Defects
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
At-Speed Transition Fault Testing With Low Speed Scan Enable
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
On Hazard-free Patterns for Fine-delay Fault Testing
ITC '04 Proceedings of the International Test Conference on International Test Conference
K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits
ITC '04 Proceedings of the International Test Conference on International Test Conference
ALAPTF: A NEW TRANSITION FAULTMODEL AND THE ATPG ALGORITHM
ITC '04 Proceedings of the International Test Conference on International Test Conference
Timing-based delay test for screening small delay defects
Proceedings of the 43rd annual Design Automation Conference
Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects
ATS '06 Proceedings of the 15th Asian Test Symposium
Supply Voltage Noise Aware ATPG for Transition Delay Faults
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
An on-chip delay measurement technique using signature registers for small-delay defect detection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Interconnect defects such as weak resistive opens, shorts, and bridges increase the path delay affected by a pattern during manufacturing test but are not significant enough to cause a failure at functional frequency. In this paper, a new faster-than-at-speed method is presented for delay test pattern application to screen small delay defects. Given a test pattern set, the technique groups the patterns into multiple subsets with close path delay distribution and determines an optimal test frequency considering both positive slack and performance degradation due to IR-drop effects. Since, the technique does not increase the test frequency to an extent that any paths exercised at the rated functional frequency may fail, it avoids any scan flip-flop masking. As most semiconductor companies currently deploy compression technologies to reduce test costs, scan-cell masking is highly undesirable for pattern modification as it would imply pattern count increase and might result in pattern regeneration. Therefore, our solution is more practical as the test engineer can run the same pattern set without any changes to the test flow other than the at-speed test frequency.