Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment
ITC '98 Proceedings of the 1998 IEEE International Test Conference
On static test compaction and test pattern ordering for scan designs
Proceedings of the IEEE International Test Conference 2001
Embedded Deterministic Test for Low-Cost Manufacturing Test
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Evaluating ATE Features in Terms of Test Escape Rates and Other Cost of Test Culprits
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Scan-Based Transition Fault Testing " Implementation and Low Cost Test Challenges
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Use of DFT Techniques In Speed Grading a 1GHz+ Microprocessor
ITC '02 Proceedings of the 2002 IEEE International Test Conference
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Meeting Nanometer DPM Requirements Through DFT
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Synchronization overhead in SOC compressed test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-frequency wrapper design and optimization for embedded cores under average power constraints
Proceedings of the 42nd annual Design Automation Conference
Value-Added Defect Testing Techniques
IEEE Design & Test
DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs
IEEE Transactions on Computers
Timing-based delay test for screening small delay defects
Proceedings of the 43rd annual Design Automation Conference
Improving Transition Delay Test Using a Hybrid Method
IEEE Design & Test
A novel framework for faster-than-at-speed delay test considering IR-drop effects
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Transition delay fault test pattern generation considering supply voltage noise in a SOC design
Proceedings of the 44th annual Design Automation Conference
Journal of Electronic Testing: Theory and Applications
Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing
Journal of Electronic Testing: Theory and Applications
Controllability of Static CMOS Circuits for Timing Characterization
Journal of Electronic Testing: Theory and Applications
Journal of Computer Science and Technology
A novel faster-than-at-speed transition-delay test method considering IR-drop effects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On the Application of Dynamic Scan Chain Partitioning for Reducing Peak Shift Power
Journal of Electronic Testing: Theory and Applications
Improved weight assignment for logic switching activity during at-speed test pattern generation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
CδIDDQ: improving current-based testing and diagnosis through modified test pattern generation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Experimental Results for Slow-speed Timing Characterization of High-speed Pipelined Datapaths
Journal of Electronic Testing: Theory and Applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Journal of Electronic Testing: Theory and Applications
AC-plus scan methodology for small delay testing and characterization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Editor's note: At-speed scan testing has demonstrated many successes in industry. One key feature is its ability to use on-chip clock for accurate timing in the application of test vectors in a tester. The authors describe new strategies where at-speed scan tests can be applied with internal PLLs. They present techniques for optimizing ATPG across multiple clock domains and propose methodologies to combine both stuck-at-fault and delay-test vectors into an effective test suite.驴Li-C. Wang, University of California, Santa Barbara