Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
Random walks in a supply network
Proceedings of the 40th annual Design Automation Conference
High-Frequency, At-Speed Scan Testing
IEEE Design & Test
On Reducing Peak Current and Power during Test
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Fast algorithms for IR drop analysis in large power grid
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Supply Voltage Noise Aware ATPG for Transition Delay Faults
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Transition delay fault test pattern generation considering supply voltage noise in a SOC design
Proceedings of the 44th annual Design Automation Conference
A Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limited Capture
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Methodology for low power test pattern generation using activity threshold control logic
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Layout-aware, IR-drop tolerant transition fault pattern generation
Proceedings of the conference on Design, automation and test in Europe
A Capture-Safe Test Generation Scheme for At-Speed Scan Testing
ETS '08 Proceedings of the 2008 13th European Test Symposium
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A scalable quantitative measure of IR-drop effects for scan pattern generation
Proceedings of the International Conference on Computer-Aided Design
Low-power skewed-load tests based on functional broadside tests
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low-power test sets under test-related primary input constraints
International Journal of Critical Computer-Based Systems
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For two-pattern at-speed scan testing, the excessive power supply noise at the launch cycle may cause the circuit under test to malfunction, leading to yield loss. This paper proposes a new weight assignment scheme for logic switching activity; it enhances the IR-drop assessment capability of the existing weighted switching activity (WSA) model. By including the power grid network structure information, the proposed weight assignment better reflects the regional IR-drop impact of each switching event. For ATPG, such comprehensive information is crucial in determining whether a switching event burdens the IR-drop effect. Simulation results show that, compared with previous weight assignment schemes, the estimated regional IR-drop profiles better correlate with those generated by commercial tools.