Estimation of Switching Noise on Power Supply Lines in Deep Sub-micron CMOS Circuits
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
ETW '03 Proceedings of the 8th IEEE European Test Workshop
Fast, Layout-Aware Validation of Test-Vectors for Nanometer-Related Timing Failures
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Supply Voltage Noise Aware ATPG for Transition Delay Faults
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Transition delay fault test pattern generation considering supply voltage noise in a SOC design
Proceedings of the 44th annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Proceedings of the Conference on Design, Automation and Test in Europe
Improved weight assignment for logic switching activity during at-speed test pattern generation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Emulating and diagnosing IR-drop by using dynamic SDF
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Journal of Electronic Testing: Theory and Applications
Power-safe application of tdf patterns to flip-chip designs during wafer test
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low-power skewed-load tests based on functional broadside tests
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Simulation Based Framework for Accurately Estimating Dynamic Power-Supply Noise and Path Delay
Journal of Electronic Testing: Theory and Applications
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Market and customer demands have continued to push the limits of CMOS performance. At-speed test has become a common method to ensure these high performance chips are being shipped to the customers fault-free. However, at-speed tests have been known to create higher-than-average switching activity, which normally is not accounted for in the design of the power supply network. This potentially creates conditions for additional delay in the chip; causing it to fail during test. In this paper, we propose a pattern compaction technique that considers the layout and gate distribution when generating transition delay fault patterns. The technique focuses on evenly distributing switching activity generated by the patterns across the layout rather than allowing high switching activity to occur in a small area in the chip that could occur with conventional delay fault pattern generation. Due to the relationship between switching activity and IR-drop, the reduction of switching will prevent large IR-drop in high demand regions while still allowing a suitable amount of switching to occur elsewhere on the chip to prevent fault coverage loss. This even distribution of switching on the chip will also result in avoiding hot-spots.