Fault modeling and simulation for crosstalk in system-on-chip interconnects
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Delay testing considering crosstalk-induced effects
Proceedings of the IEEE International Test Conference 2001
Test generation for crosstalk-induced faults: framework and computational results
ATS '00 Proceedings of the 9th Asian Test Symposium
Estimation of Switching Noise on Power Supply Lines in Deep Sub-micron CMOS Circuits
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Testing SoC Interconnects for Signal Integrity Using Boundary Scan
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Use of DFT Techniques In Speed Grading a 1GHz+ Microprocessor
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Test Generation for Crosstalk-Induced Delay in Integrated Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
ICCD '03 Proceedings of the 21st International Conference on Computer Design
On Generating Pseudo-Functional Delay Fault Tests for Scan Designs
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design
ITC '04 Proceedings of the International Test Conference on International Test Conference
On identifying functionally untestable transition faults
HLDVT '04 Proceedings of the High-Level Design Validation and Test Workshop, 2004. Ninth IEEE International
Supply Voltage Noise Aware ATPG for Transition Delay Faults
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Test-Pattern Grading and Pattern Selection for Small-Delay Defects
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
Layout-aware, IR-drop tolerant transition fault pattern generation
Proceedings of the conference on Design, automation and test in Europe
Layout-Aware Pattern Generation for Maximizing Supply Noise Effects on Critical Paths
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analytical models for crosstalk excitation and propagation in VLSI circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Critical path selection for delay fault testing based upon a statistical timing model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
First-Order Incremental Block-Based Statistical Timing Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Power supply noise and crosstalk are the two major noise sources that are pattern dependent and negatively impact signal integrity in digital integrated circuits. These noise sources play a greater role in sub-65nm technologies and may cause timing failures and reliability problems in a design; thus must be carefully taken into consideration during test pattern generation and validation. In this paper, we propose a novel method to evaluate path-delay fault test patterns in terms of their ability to cause excess delay on targeted critical paths. It quantifies the noises with a pattern quality value (Q) using the activated aggressor gates and nets information. The proposed method offers design engineers a quick approach to evaluate the critical paths in static timing analysis (STA) and silicon to improve timing margin strategies. By evaluating the failed test pattern, the proposed method can be used to help identify the root cause during failure analysis. Simulation results demonstrate the efficiency and effectiveness of the pattern grading procedure.