Test-Pattern Grading and Pattern Selection for Small-Delay Defects

  • Authors:
  • Mahmut Yilmaz;Krishnendu Chakrabarty;Mohammad Tehranipoor

  • Affiliations:
  • -;-;-

  • Venue:
  • VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
  • Year:
  • 2008

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Abstract

Timing-related defects are becoming increasingly important in nanometer technology designs. Small delay variations induced by crosstalk, process variations, power-supply noise, as well as resistive opens and shorts can potentially cause timing failures in a design, thereby leading to quality and reliability concerns. We present a test-grading technique to leverage the method of output deviations for screening small-delay defects (SDDs). A new gate-delay defect probability measure is defined to model delay variations for nanometer technologies. The proposed technique intelligently selects the best set of patterns for SDD detection from an n-detect pattern set generated using timing-unaware automatic test-pattern generation (ATPG). It offers significantly lower computational complexity and it excites a larger number of long paths compared to previously proposed timing-aware ATPG methods. We show that, for the same pattern count, the selected patterns are more effective than timing-aware ATPG for detecting small delay defects caused by resistive shorts, resistive opens, and process variations.