Line coverage of path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
Proceedings of the 39th annual Design Automation Conference
An Introduction to Numerical Methods with MATLAB
An Introduction to Numerical Methods with MATLAB
Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs
Proceedings of the IEEE International Test Conference
Evaluation of the Quality of N-Detect Scan ATPG Patterns on a Processor
ITC '04 Proceedings of the International Test Conference on International Test Conference
ALAPTF: A NEW TRANSITION FAULTMODEL AND THE ATPG ALGORITHM
ITC '04 Proceedings of the International Test Conference on International Test Conference
Timing-based delay test for screening small delay defects
Proceedings of the 43rd annual Design Automation Conference
Test-Pattern Grading and Pattern Selection for Small-Delay Defects
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
Dynamic Compaction for High Quality Delay Test
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
Critical Path Selection for Delay Test Considering Coupling Noise
ETS '08 Proceedings of the 2008 13th European Test Symposium
Effective and Efficient Test Pattern Generation for Small Delay Defect
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
Statistical Timing Analysis in the Presence of Signal-Integrity Effects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient Pattern Generation for Small-Delay Defects Using Selection of Critical Faults
Journal of Electronic Testing: Theory and Applications
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Testing for small-delay defects (SDDs) is necessary to ensure the quality and reliability of high-performance integrated circuits fabricated with the latest technologies. These timing defects can be caused by process variations, crosstalk, and power-supply noise, as well as by physical defects such as resistive opens and shorts. Timing-aware ATPG tools have been developed for SDD detection. However, they only use static timing analysis reports for path-length calculation and neglect important parameters such as process variations, crosstalk, and power-supply noise, which can induce small delays into the circuit and impact the timing of targeted paths. In this paper, we present an efficient pattern evaluation and selection procedure for screening SDDs that are caused by physical defects and by delays added to paths by process variations and crosstalk. In this procedure, the best patterns for SDDs are selected from a large repository test set. Experimental results demonstrate that our method sensitizes more long paths and detects more SDDs with a much smaller pattern count compared with a commercial timing-aware ATPG tool.