A data capturing method for buses on chip
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Proceedings of the Conference on Design, Automation and Test in Europe
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Signal-integrity effects have significant impacts on very large-scale-integration performance variation and must be taken into account in statistical timing analysis. In this paper, we study the signal-propagation-delay variation that is induced by crosstalk aggressor signals. We establish a functional relationship between the signal propagation delay and the crosstalk aggressor signal alignment by deterministic circuit simulation and derive closed-form formulas for the statistical distributions of output signal arrival times. Our proposed method can be smoothly integrated into a static timing analyzer, wherein runtime is dominated by sampling the deterministic delay calculation, while probabilistic computation and updating take constant time. Experimental results based on the 1000- global interconnect structures in Berkeley Predictive Technology Model 70-nm technology and industry designs in 130-nm technology show that lack of statistical crosstalk aggressor signal alignment consideration could lead to up to 114.65% (71.26%) differences in interconnect-delay means (standard deviations) and 159.4% (147.4%) differences in gate-delay means (standard deviations). By contract, the method in our earlier work gives within 1.28% (3.38%) mismatch in interconnect output signal arrival time means (standard deviations) and within 2.57% (3.86%) mismatch in gate output signal arrival time means (standard deviations), respectively.