Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Gate sizing for constrained delay/power/area optimization
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Bus encoding for low-power high-performance memory systems
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Self-Checking Detection and Diagnosis of Transient, Delay, and Crosstalk Faults Affecting Bus Lines
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Route packets, not wires: on-chip inteconnection networks
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Coupling-driven bus design for low-power application-specific systems
Proceedings of the 38th annual Design Automation Conference
Odd/even bus invert with two-phase transfer for buses with coupling
Proceedings of the 2002 international symposium on Low power electronics and design
Coupling-driven signal encoding scheme for low-power interface design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Bus encoding to prevent crosstalk delay
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
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Repeater Insertion To Minimise Delay In Coupled Interconnects
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A Bus Encoding Technique for Power and Cross-talk Minimization
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New ECC for Crosstalk Impact Minimization
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IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
Statistical modeling of cross-coupling effects in VLSI interconnects
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ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Small-Delay Defect Detection in the Presence of Process Variations
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IEEE Design & Test
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Exploiting ECC Redundancy to Minimize Crosstalk Impact
IEEE Design & Test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Data bus inversion in high-speed memory applications
IEEE Transactions on Circuits and Systems II: Express Briefs
Bus encoding for total power reduction using a leakage-aware buffer configuration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Post global routing crosstalk synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Buffer insertion for noise and delay optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A postprocessing algorithm for crosstalk-driven wire perturbation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Repeater scaling and its impact on CAD
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical Timing Analysis in the Presence of Signal-Integrity Effects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, a new data reading technique for a bus of lines is proposed for fast operation. The proposed method utilizes multiple reference voltages available within a line's receiving logic and the initial conditions of wires in order to determine early and accurately the transmitted data of the current cycle. The presented technique does not require repeater insertion for reasonably long lines and it can significantly accelerate signal propagaion. Experimental results are given in the 65 nm CMOS process for interconnects of various lengths.