Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power encodings for global communication in CMOS VLSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Partial bus-invert coding for power optimization of system level bus
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Encodings for high-performance for energy-efficient signaling
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Analysis and implementation of charge recycling for deep sub-micron buses
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Odd/even bus invert with two-phase transfer for buses with coupling
Proceedings of the 2002 international symposium on Low power electronics and design
Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A data capturing method for buses on chip
IEEE Transactions on Circuits and Systems Part I: Regular Papers
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We propose various low-latency spatial encoder circuits based on bus-invert coding for reducing peak energy and current in on-chip buses with minimum penalty on total latency. The encoders are implemented in dual-rail domino logic with interfaces for static inputs and static buses. A spatial and temporally encoded dynamic bus technique is also proposed for higher performance targets. Comparisons to standard on-chip buses of various lengths with optimal repeater configurations at the 130nm node show the energy-delay and peak current-delay design space in which the different encoder circuits are beneficial. A 9mm spatially encoded static bus exhibits peak energy gains beyond that achievable through repeater optimization for a single cycle operation at 1GHz, with delay and energy overhead of the encoding included. For throughput constrained buses, the spatially encoded static bus can provide up to 31% reduction in peak energy, while the spatially and temporally encoded dynamic bus yields peak current reductions of more than 50% for all bus lengths.