Power reduction techniques for a spread spectrum based correlator
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Power estimation for architectural exploration of HW/SW communication on system-level buses
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Influence of caching and encoding on power dissipation of system-level buses for embedded systems
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Synthesis of low-overhead interfaces for power-efficient communication over wide buses
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
System-level power optimization: techniques and tools
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Power optimization of system-level address buses based on software profiling
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
System-level power optimization: techniques and tools
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Narrow bus encoding for low power systems
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
A$^{\mbox{\huge\bf 2}}$BC: adaptive address bus coding for low power deep sub-micron designs
Proceedings of the 38th annual Design Automation Conference
Modeling and minimization of interconnect energy dissipation in nanometer technologies
Proceedings of the 38th annual Design Automation Conference
Energy reduction in queues and stacks by adaptive bitwidth compression
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Encodings for high-performance for energy-efficient signaling
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Low-energy for deep-submicron address buses
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Low power address encoding using self-organizing lists
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Analysis and implementation of charge recycling for deep sub-micron buses
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Bus energy minimization by transition pattern coding (TPC) in deep sub-micron technologies
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A bus energy model for deep submicron technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power protocol: reducing power dissipation on off-chip data buses
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Weight-Based Bus-Invert Coding for Low-Power Applications
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Adaptive low-power address encoding techniques using self-organizing lists
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
A dictionary-based en/decoding scheme for low-power data buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Spatial encoding circuit techniques for peak power reduction of on-chip high-performance buses
Proceedings of the 2004 international symposium on Low power electronics and design
DVS for On-Chip Bus Designs Based on Timing Error Correction
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
SILENT: serialized low energy transmission coding for on-chip interconnection networks
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Multi-parametric improvements for embedded systems using code-placement and address bus coding
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Optimizing bus energy consumption of on-chip multiprocessors using frequent values
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Parallel, distributed and network-based processing
Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
A new array architecture for signed multiplication using Gray encoded radix-2m operands
Integration, the VLSI Journal
Proceedings of the conference on Design, automation and test in Europe
Journal of Electronic Testing: Theory and Applications
Energy reduction through crosstalk avoidance coding in networks on chip
Journal of Systems Architecture: the EUROMICRO Journal
Power consumption of fault tolerant busses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dual-rail transition logic: A logic style for counteracting power analysis attacks
Computers and Electrical Engineering
SAMBA-bus: A high performance bus architecture for system-on-chips
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Systems Architecture: the EUROMICRO Journal
Approximate arithmetic coding for bus transition reduction in low power designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Utilizing the effect of relative delay on energy dissipation in low-power on-chip buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Context-independent codes for off-chip interconnects
PACS'04 Proceedings of the 4th international conference on Power-Aware Computer Systems
Partial bus-invert bus encoding schemes for low-power DSP systems considering inter-wire capacitance
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Techniques to enhance the resistance of precharged busses to differential power analysis
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
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Technology trends and especially portable applications are adding a third dimension (power) to the previously two-dimensional (speed, area) VLSI design space. A large portion of power dissipation in high performance CMOS VLSI is due to the inherent difficulties in global communication at high rates and we propose several approaches to address the problem. These techniques can be generalized at different levels in the design process. Global communication typically involves driving large capacitive loads which inherently require significant power. However, by carefully choosing the data representation, or encoding, of these signals, the average and peak power dissipation can be minimized. Redundancy can be added in space (number of bus lines), time (number of cycles) and voltage (number of distinct amplitude levels). The proposed codes can be used on a class of terminated off-chip board-level buses with level signaling, or on tristate on-chip buses with level or transition signaling.