Low-power encodings for global communication in CMOS VLSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Digital systems engineering
Architectures and synthesis algorithms for power-efficient bus interfaces
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Energy-reliability trade-off for NoCs
Networks on chip
Spatial encoding circuit techniques for peak power reduction of on-chip high-performance buses
Proceedings of the 2004 international symposium on Low power electronics and design
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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