Fault-tolerant computing: theory and techniques; Vol. 2
Fault-tolerant computing: theory and techniques; Vol. 2
Automatic sizing of power/ground (P/G) networks in VLSI
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power supply noise analysis methodology for deep-submicron VLSI chip design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Digital systems engineering
Working-zone encoding for reducing the energy in microprocessor address buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis of performance impact caused by power supply noise in deep submicron devices
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A coding framework for low-power address and data busses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Bus crosstalk fault-detection capabilities of error-detecting codes for on-line testing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-string on-chip signaling techniques: effectiveness and robustness
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Toward achieving energy efficiency in presence of deep submicron noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimization of error detecting codes for the detection of crosstalk originated errors
Proceedings of the conference on Design, automation and test in Europe
Encodings for high-performance for energy-efficient signaling
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
An adaptive low-power transmission scheme for on-chip networks
Proceedings of the 15th international symposium on System Synthesis
Coupling-driven signal encoding scheme for low-power interface design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Bus energy minimization by transition pattern coding (TPC) in deep sub-micron technologies
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Low Power Chip Interface Based on Bus Data Encoding with Adaptive Code-Book Method
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Weight-Based Codes and Their Application to Concurrent Error Detection of Multilevel Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Extension of the Working-Zone-Encoding Method to Reduce the Energy on the Microprocessor Data Bus
ICCD '98 Proceedings of the International Conference on Computer Design
Low Power Error Resilient Encoding for On-Chip Data Buses
Proceedings of the conference on Design, automation and test in Europe
An Adaptive Dictionary Encoding Scheme for SOC Data Buses
Proceedings of the conference on Design, automation and test in Europe
On-line detection of bridging and delay faults in functional blocks of CMOS self-checking circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Architectures and synthesis algorithms for power-efficient bus interfaces
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Decoupling capacitance allocation and its application to power-supply noise-aware floorplanning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Architecture-Driven reliability and energy optimization for complex embedded systems
QoSA'10 Proceedings of the 6th international conference on Quality of Software Architectures: research into Practice - Reality and Gaps
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Solutions for combined energy minimization and communication reliability control have to be developed for SoC networks. Redundant encodings and error-resilient protocols create new degrees of freedom for trading off energy against realiability and viceversa. In this chapter, the theoretical framework for energy and realiability analysis is introduced and several error control and recovery strategies are investigated in a realistic SoC setting. Furthermore, the chapter provides guidelines and methods to select the most appropriate error control scheme for a given reliability and/or energy efficiency constraint.