Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Embedded power supply for low-power DSP
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
The simulation and evaluation of dynamic voltage scaling algorithms
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
High-performance communication networks (2nd ed.)
High-performance communication networks (2nd ed.)
Low-string on-chip signaling techniques: effectiveness and robustness
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Toward achieving energy efficiency in presence of deep submicron noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automatic performance setting for dynamic voltage scaling
Proceedings of the 7th annual international conference on Mobile computing and networking
Soft digital signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Dynamic Power Management: Design Techniques and CAD Tools
Dynamic Power Management: Design Techniques and CAD Tools
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Low Power Error Resilient Encoding for On-Chip Data Buses
Proceedings of the conference on Design, automation and test in Europe
Power-efficient Interconnection Networks: Dynamic Voltage Scaling with Links
IEEE Computer Architecture Letters
A survey of techniques for energy efficient on-chip communication
Proceedings of the 40th annual Design Automation Conference
PowerHerd: dynamic satisfaction of peak power constraints in interconnection networks
ICS '03 Proceedings of the 17th annual international conference on Supercomputing
Leakage power modeling and optimization in interconnection networks
Proceedings of the 2003 international symposium on Low power electronics and design
Energy-reliability trade-off for NoCs
Networks on chip
A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
How Can System-Level Design Solve the Interconnect Technology Scaling Problem?
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Reliable communication in systems on chips
Proceedings of the 41st annual Design Automation Conference
Adapative Error Protection for Energy Efficiency
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Power-aware communication optimization for networks-on-chips with voltage scalable links
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
DVS for On-Chip Bus Designs Based on Timing Error Correction
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Quality-of-service and error control techniques for mesh-based network-on-chip architectures
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
A robust self-calibrating transmission scheme for on-chip networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Software-directed power-aware interconnection networks
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Analysis of Error Recovery Schemes for Networks on Chips
IEEE Design & Test
Deployment of Better Than Worst-Case Design: Solutions and Needs
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Compiler-directed channel allocation for saving power in on-chip networks
Conference record of the 33rd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Soft self-synchronising codes for self-calibrating communication
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Core Network Interface Architecture and Latency Constrained On-Chip Communication
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Reducing NoC energy consumption through compiler-directed channel voltage scaling
Proceedings of the 2006 ACM SIGPLAN conference on Programming language design and implementation
Proceedings of the 43rd annual Design Automation Conference
Run-time reconfigurabilility and other future trends
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Software-directed power-aware interconnection networks
ACM Transactions on Architecture and Code Optimization (TACO)
Profile-driven energy reduction in network-on-chips
Proceedings of the 2007 ACM SIGPLAN conference on Programming language design and implementation
The Journal of Supercomputing
Software-directed combined cpu/link voltage scaling fornoc-based cmps
SIGMETRICS '08 Proceedings of the 2008 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Variation tolerant NoC design by means of self-calibrating links
Proceedings of the conference on Design, automation and test in Europe
Self-Adaptive Networked Entities for Building Pervasive Computing Architectures
ICES '08 Proceedings of the 8th international conference on Evolvable Systems: From Biology to Hardware
Highly-cited ideas in system codesign and synthesis
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
A variable frequency link for a power-aware network-on-chip (NoC)
Integration, the VLSI Journal
An outlook on design technologies for future integrated systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Quality-of-service and error control techniques for mesh-based network-on-chip architectures
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
An overview of achieving energy efficiency in on-chip networks
International Journal of Communication Networks and Distributed Systems
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Intelligent on/off dynamic link management for on-chip networks
Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
Application-driven end-to-end traffic predictions for low power NoC design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy-aware fault-tolerant network-on-chips for addressing multiple traffic classes
Microprocessors & Microsystems
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Systems-on-Chip (SoC) are evolving toward complex heterogeneous multiprocessors made of many predesigned macrocells or subsystems with application-specific interconnections. Intra-chip interconnects are thus becoming one of the central elements of SoC design and pose conflicting goals in terms of low energy per transmitted bit, guaranteed signal integrity, and ease of design. This work introduces and shows first results on a novel interconnect system which uses low-swing signalling, error detection codes, and a retransmission scheme; it minimises the interconnect voltage swing and frequency subject to workload requirements and S/N conditions. Simulation results show that tangible savings in energy can be attained while achieving at the same time more robustness to large variations in actual workload, noise, and technology quality (all quantities easily mispredicted in very complex systems and advanced technologies). It can be argued that traditional worst-case correct-by-design paradigm will be less and less applicable in future multibillion transistor SoC and deep sub-micron technologies; this work represents a first example towards robust adaptive designs.