A Fault-Tolerant FFT Processor
IEEE Transactions on Computers
Algorithm-Based Fault Tolerance on a Hypercube Multiprocessor
IEEE Transactions on Computers
Precomputation-based sequential logic optimization for low power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Statistical estimation of the switching activity in digital circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Architectural power analysis: the dual bit type method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Digital signal processing (3rd ed.): principles, algorithms, and applications
Digital signal processing (3rd ed.): principles, algorithms, and applications
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Noise in deep submicron digital design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Exploring the design space of mixed swing QuadRail for low-power digital circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Embedded power supply for low-power DSP
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Interconnect in high speed designs: problems, methodologies and tools
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Getting to the bottom of deep submicron
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Energy-efficiency in presence of deep submicron noise
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Conquering Noise in Deep-Submicron Digital ICs
IEEE Design & Test
Low-power adaptive filter architectures and their application to51.84 Mb/s ATM-LAN
IEEE Transactions on Signal Processing
An approach for multilevel logic optimization targeting low power
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reliable and energy-efficient digital signal processing
Proceedings of the 39th annual Design Automation Conference
An adaptive low-power transmission scheme for on-chip networks
Proceedings of the 15th international symposium on System Synthesis
Energy-efficiency bounds for deep submicron VLSI systems in the presence of noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power MIMO signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Adapative Error Protection for Energy Efficiency
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Reliable low-power digital signal processing via reduced precision redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A robust self-calibrating transmission scheme for on-chip networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Soft self-synchronising codes for self-calibrating communication
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Energy-efficient soft error-tolerant digital signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy-efficient motion estimation using error-tolerance
Proceedings of the 2006 international symposium on Low power electronics and design
On the selection of arithmetic unit structure in voltage overscaled soft digital signal processing
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Trends in energy-efficiency and robustness using stochastic sensor network-on-a-chip
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Error-resilient low-power Viterbi decoders
Proceedings of the 13th international symposium on Low power electronics and design
Variable latency speculative addition: a new paradigm for arithmetic circuit design
Proceedings of the conference on Design, automation and test in Europe
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
Error-resilient motion estimation architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low power robust signal processing
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Experimental analysis of sequence dependence on energy saving for error tolerant image processing
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Design of voltage overscaled low-power trellis decoders in presence of process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Error-resilient low-power Viterbi decoder architectures
IEEE Transactions on Signal Processing
Checksum-based probabilistic transient-error compensation for linear digital systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On improving the algorithmic robustness of a low-power FIR filter
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Computation error analysis in digital signal processing systems with overscaled supply voltage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 47th Design Automation Conference
Computation as estimation: a general framework for robustness and energy efficiency in SoCs
IEEE Transactions on Signal Processing
Stochastic networked computation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IMPACT: imprecise adders for low-power approximate computing
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Error-resilient low-power DSP via path-delay shaping
Proceedings of the 48th Design Automation Conference
Inexact computing for ultra low-power nanometer digital circuit design
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
MACACO: modeling and analysis of circuits for approximate computing
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the 9th conference on Computing Frontiers
Modeling and synthesis of quality-energy optimal approximate adders
Proceedings of the International Conference on Computer-Aided Design
Synthesizing Parsimonious Inexact Circuits through Probabilistic Design Techniques
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Probabilistic Embedded Computing
High performance reliable variable latency carry select addition
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
An energy efficient approximate adder with carry skip for error resilient neuromorphic VLSI systems
Proceedings of the International Conference on Computer-Aided Design
Approximate logic synthesis under general error magnitude and frequency constraints
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 0.01 |
In this paper, we propose a framework for low-energy digital signalprocessing (DSP), where the supply voltage is scaled beyond thecritical voltage imposed by the requirement to match the criticalpath delay to the throughput. This deliberate introduction ofinput-dependent errors leads to degradation in the algorithmicperformance, which is compensated for via algorithmicnoise-tolerance (ANT) schemes. The resulting setup thatcomprises of the DSP architecture operating at subcritical voltageand the error control scheme is referred to as soft DSP. Theeffectiveness of the proposed scheme is enhanced when arithmeticunits with a higher "delay imbalance" are employed. Aprediction-based error-control scheme is proposed to enhance theperformance of the filtering algorithm in the resence of errors dueto soft computations. For a frequency selective filter, it is shownthat the proposed scheme provides 60-81% reduction in energydissipation for filter bandwidths up to 0.5π (where 2πcorresponds to the sampling frequency fs) overthat achieved via conventional architecture and voltage scaling,with a maximum of 0.5-dB degradation in the output signal-to-noiseratio (SNRO). It is also shown that the proposedalgorithmic noise-tolerance schemes can also be used to improve theperformance of DSP algorithms in presence of bit-error rates of upto 10−3 due to deep submicron (DSM) noise.